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Preliminary Data Sheet PD60214 Rev B
IR20153S & (PbF)
HIGH SIDE DRIVER WITH RECHARGE
Features
* * * * * * * * * * Floating channel designed for bootstrap operation
Fully operational up to 150V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 5V to 20V Undervoltage lockout Internal recharge FET for bootstrap refresh Internal deadtime of 11s and 0.8s CMOS Schmitt-triggered input logic Output out of phase with input Reset input Split pull-up and pull-down gate drive pins Also available LEAD-FREE (PbF)
Product Summary
VOFFSET IO+/VOUT ton/off 150V max. 400mA @ VBS=7V, 1.5A @ VBS=16V 5-20V 1.0 and 0.3 s
Description
The IR20153S is a high voltage, high speed power MOSFET driver . Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS output down to 3.3V. The output driver features a high pulse current buffer stage designed for minimum cross-conduction. The floating channel can be used to drive an N-channel power MOSFET in the high or low side configuration which operates up to 150 volts.
Package
8-Lead SOIC
Typical Connection
up to 150V
VCC IN
VCC IN GND
VB HOH HOL VS
RESET
RESET
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
Load
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1
IR20153S & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND, all currents are defined positive into any lead. This is a stress only rating and operation of the device at these or any conditions exceeding those indicated in the operational sections of this specifications is not implied.
Symbol
VB VS VHO VCC VIN dV/dt TJ TS TL
Definition
High side driver output stage voltage High side floating supply offset voltage Output voltage gate high connection Low side fixed supply voltage Input voltage (IN and RESET) Allowable offset voltage slew rate Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
Min.
-5.0 - 8.0 VS - 0.3 -0.3 -- -55 -55 --
Max.
170 150 VB + 0.3 25 -0.3 50 150 150 300
Units
V
VCC +0.3 V/nsec
C
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 2. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND. The VS offset rating is tested with all suppliers biased at Vcc=5V and VBS=7V.
Symbol
VB VS VHO VCC VIN TA
Definition
High side driver output stage voltage High side floating supply offset voltage Output voltage gate high connection Supply voltage Input voltage (IN and RESET) Ambient temperature
Min.
VS + 5 -1.6 VS 5 0 -55
Max.
VS + 20 150 VB 20 Vcc 150
Units
V
C
2
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IR20153S & (PbF)
Electrical Characteristics
Unless otherwise specified, VCC = 5V, VBS = 7V, VS = 0V, IN = 0V, RES = 5V, load R = 50, C = 6.8nF (see Figure 3). Unless otherwise noted, these specifications apply for an operating ambient temperature of TA =25C.
Symbol
VCCUV+ VCCUVVCCUVHYS IQCC VBSUV+ VBSUVVBSUVHYS IQBS1 IQBS2
Definition
VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage lockout hysteresis VCC supply current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VBS supply undervoltage lockout hysteresis VBS supply current VBS supply current
Min. Typ. Max. Units Test Conditions
-- 2.5 0.01 -- -- 2.5 0.01 -- -- -- -- 0.3 -- -- -- 0.3 -- -- 4.3 -- 0.60 400 4.3 -- 0.60 100 200 uA V VCC = 3.6V & 6.5V VBS rising from 0V VBS dropping from 5V V VCC rising from 0V VCC dropping from 5V
VCC Supply Characteristics
VBS Supply Characteristics
A A
static mode, VBS = 7V, IN = 0V or 5V static mode, VBS = 16V, IN = 0V or 5V
VB. VS Supply Characteristics
ILK Io+1 Io+2 tr1 tr2 Io-1 Io-2 tf1 tf2 ton toff tres,off Offset supply leakage current Peak output source current Peak output source current Output rise time Output rise time Peak output sink current Peak output sink current Output fall time Output fall time Input-to-Output Turn-on propogation delay (50% input level to 10% output level) Input-to-Output Turn-off propogation delay (50% input level to 90% output level) RES-to-Output Turn-off propogation delay (50% input level to 90% [tphl] output levels) -- 0.3 0.9 -- 0.3 0.9 -- 250 800 -- -- 250 800 -- -- -- -- 400 1500 0.2 0.1 400 1500 0.2 0.1 1.0 50 -- -- 0.4 0.2 -- -- 0.4 0.2 2.0
A
mA mA
VB = VS = 150V
Gate Driver Characteristics
VBS = 16V VBS = 16V IN = 5V VBS = 16V, IN = 5V IN = 5V VBS = 16V, IN = 5V
sec sec
mA mA
sec sec sec sec sec
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IR20153S & (PbF)
Electrical Characteristics
Unless otherwise specified, VCC = 5V, VBS = 7V, VS = 0V, IN = 0V, RES = 5V, load R = 50, C = 6.8nF (see Figure 3). Unless otherwise noted, these specifications apply for an operating ambient temperature of TA =25C.
Symbol
tres,on
Definition
RES-to-Output Turn-On Propogation Delay (50% input level to 10% [tplh] output levels)
Min. Typ. Max. Units Test Conditions
1.0 2.0
Gate Driver Characteristics VCC Supply Characteristics cont.
sec
Input Characteristics
VINH VINL RIN VH_RES VL_RES RRES ton_rech toff_rech VRECH DTHOFF DTHON High Logic Level Input Threshold Low Logic Level Input Threshold High Logic Level Input Resistance High Logic Level RES Input Threshold Low Logic Level RES Input Threshold High Logic Level RES Input Resistance Recharge Transistor Turn-On Propogation Delay Recharge Transistor Turn-Off Propogation Delay Recharge Output Transistor On-State Voltage Drop High Side Turn-Off to Recharge gate Turn-On Recharge gate Turn-Off to High Side Turn-On0. 3 40 3 40 7 7 0.4 100 100 11 0.3 11 0.8 1.4 220 1.4 220 15 0.9 1.2 15 1.5 V V k V V k
Recharge Characteristics (see Figure 3a)
sec sec
V
VS = 5V IS = 1mA, IN = 5V
Deadtime Characteristics sec sec
4
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IR20153S & (PbF)
A True table for Vcc, VBS, RESET, IN, HO and RechFET is shown as follows. This truth table is for ACTIVE LOW IN. RESETINRechFET Vcc VBS HO
VccUVLO+ >VccUVLO+ >VccUVLO+ >VccUVLO+ >VccUVLO+ >VccUVLO+ >VccUVLO+ >VccUVLO+ VBSUVLO+ >VBSUVLO+ >VBSUVLO+ >VBSUVLO+ VBSUVLO+ >VBSUVLO+ >VBSUVLO+ >VBSUVLO+ HIGH HIGH LOW LOW HIGH HIGH LOW LOW HIGH HIGH LOW LOW HIGH HIGH LOW LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF OFF ON ON ON ON ON ON ON ON ON OFF ON ON ON1 OFF1 ON1 ON1
RESET = HIGH indicates that high side MOSFET is allowed to be turned on. RESET = LOW indicates that high side MOSFET is OFF. IN = LOW indicates that high side MOSFET is on. IN = HIGH indicates that high side MOSFET is off. RechFET = ON indicates that the recharge MOSFET is on. RechFET = OFF indicates that the recharge MOSFET is off. 1 Note: Refer to the RESET functionality graph of Figure 7, for VCC and VBS voltage ranges under which the functionality is normal. www.irf.com 5
IR20153S & (PbF)
Functional Block Diagram
VB
UV DETECT HV LEVEL SHIFT VCC PULSE FILTER
R R S
Q HOH HOL
UV DETECT
PULSE GEN
VS
RESET LOGIC IN DELAYS RECHARGE SWITCH
Lead Definitions and Assignments
Symbol Description
VCC I INGND RESET VS HOL HOH VB Driver Supply Driver Control Signal Input Ground Driver Enable Signal Input MOSFET Source Connection MOSFET Gate Low Connection MOSFET Gate High Connection Driver Output Stage Supply
1 2 3 4
VCC INGND RESET-
VB HOH HOL VS
8 7 6 5
8-Lead SOIC
6
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IR20153S & (PbF)
INRESET-
HO-VS
Figure 1. Input/Output Functional Diagram
IN RES HOH,L
Tres,on Tres,off
Figure 1a. Reset Timing Diagram
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IR20153S & (PbF)
IN RESET
5V
Vs HOH,L T on Recharge FET OFF T off_rech Ton_rech T off ON
Figure 2. Input/Output Timing Diagram
90%
90%
10% Tr T f
10%
Figure 2a. Output Timing Diagram
8
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IR20153S & (PbF)
5V
7V
VCC INGND RESET-
VB HOH HOL VS
50ohm
50ohm
6.8nF
Figure 3. Switching Time Test Circuit
5V
7V
VCC INGND RESET-
VB HOH HOL VS
50ohm
50ohm
6.8nF
5V
Figure 3a. Ton_rech and Toff_rech Test Circuit
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IR20153S & (PbF)
3.4 3.2 Vinth+ (V) VINth- (V) 4.4 4.7 5 5.3 5.6 5.9 Vsupply (V) 6.2 6.5 3 2.8 2.6 2.4 2.2
2.8 2.5 2.2 1.9 1.6 1.3 4.4 4.7 5 5.3 5.6 5.9 Vsupply (V) 6.2 6.5
Figure 4. Positive Input and Reset Threshold Voltage vs. Vsupply
Figure 5. Negative Input and Reset Threshold Voltage vs. Vsupply
160 140 RIN (kohm) 120 I (mA) -25 0 25 50 T ( oC ) 75 100 125 100 80 60 40 -50
2.2 1.9 1.6 1.3 1 0.7 0.4 0.6 0.8 1 V (V) Figure 7. Recharge FET I-V Curve 1.2 1.4
Figure 6. Input and Reset Impedance vs. Tem perature
10
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IR20153S & (PbF)
35 30 25 VBS (V) 20 15 10 5 0 3.4 3.8 4.2 VCC (V) Figure 8. Reset Functionality 4.6 5
125oC 25oC -40oC
2200 Output Sink Current (mA) 1800 1400 1000 600 200 5 10 VBS (V) Figure 9. Output Sink Current vs. VBS 15 20
125C -40C
This graph explains the functionality limitation as a function of VCC, VBS and temperature. Each curve on the graph represents VCC Vs. VBS, for a particular temperature. For each particular temperature and VCC, the output is non-functional for any value of VBS above the drawn curve. But for any value of VBS below the curve the functionality is fine.
Turn-on Propagation Delay (ns) 700 Output Source Current (mA) 650 600 550 500 450 400 -50 1300 1200 1100 1000 900 800 -50
0
50 Temperature C) (o
100
150
0
50
o
100
150
Temperature ( C) Figure 11. Turn-on Propagation Delay vs. Tem perature, VBS=7V
Figure 10. Output Source Current vs. Tem perature, VBS=7V
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IR20153S & (PbF)
RES-to-Output Turn-on Propagation Delay (ns)
Turn-off Propagation Delay (ns)
320
1300 1200 1100 1000 900 800 -50
280
240
200 -50
0
50 Temperature ( C)
o
100
150
0
50
o
100
150
Temperature ( C)
Figure 12. Turn-off Propagation Delay vs. Tem perature, VBS=7V
Figure 13. RES-to-Output Turn-on Propagation Delay vs. Tem perature, VBS=7V
High Logic Level Input Resistance (kohm
RES-to-Output Turn-off Propagation Delay (ns)
350 300 250 200 150 100 50 -50
200 175 150 125 100 75 50 -50
0
50
100
150
0
50 Temperature (oC)
100
150
Temperature (oC) Figure 14. RES-to-Output Turn-off Propagation Delay vs. Tem perature, VBS=7V
Figure 15. High Logic Level Input Resistance vs. Tem perature, VBS=7V
12
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IR20153S & (PbF)
High Logic Level RES Input Resistance (kohm)
Recharge Transistor Turn-on Propagation Delay (us)
175 150 125 100 75 50 -50
12 11 10 9 8 -50
0
50
o
100
150
0
50
o
100
150
Temperature ( C) Figure 16. High Logic Level RES Input Resistance vs. Tem perature, VBS=7V
Temperature ( C)
Figure 17. Recharge Transistor Turn-on Propagation Delay vs. Temperature, VBS=7V
Recharge Transistor Turn-off Propagation Delay (ns)
320 300 280 260 240 220 200 -50
High Side Turn-off to Recharge Gate Turn on (us)
11 10.5 10 9.5 9 8.5 8 -50
0
50
100
150
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 18. Recharge Transistor Turn-off Propagation Delay vs. Tem perature, VBS=7V
Figure 19. High Side Turn-off to Recharge Gate Turn-on vs. Tem perature, VBS=7V
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IR20153S & (PbF)
Recharge Gate Turn-off to High Side Turn on (ns)
1200 1000
800 600 400 -50
0
50
100
150
Temperature (oC)
Figure 20. Recharge Gate Turn-off to High Side Turn-on vs. Tem perature, VBS=7V
Case outline
D A 5 B
FOOTPRINT 8X 0.72 [.028]
DIM A b c D
INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
6 E
8
7
6
5 H 0.25 [.010] A
E
6.46 [.255]
1
2
3
4
e e1 H K L
8X 1.78 [.070]
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e e1
3X 1.27 [.050]
y
A C 0.10 [.004] y
K x 45
8X b 0.25 [.010]
NOTES:
A1 CAB
8X L 7
8X c
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE.
8-Lead SOIC
14
01-6027 01-0021 11 (MS-012AA)
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IR20153S & (PbF)
LEADFREE PART MARKING INFORMATION
Part number
IRxxxxxx YWW? ?XXXX
Lot Code (Prod mode - 4 digit SPN code) IR logo
Date code
Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released
Assembly site code Per SCOP 200-002
ORDER INFORMATION
Basic Part (Non-Lead Free) 8-Lead SOIC IR20153S order IR20153S Leadfree Part 8-Lead SOIC IR20153S order IR20153SPbF
Thisproduct has been designed and qualified for the industrial market. Qualification Standards can be found on IR's Web Site http://www.irf.com Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 10/25/2004
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